With the development of semiconductor technology, semiconductor products are developed to have low power consumption and low cost, thus, a power-supply voltage of a memory is relatively low, such as 2.5V and 1.8V. However, to realize reading and writing of stored information, a voltage for programming and erasing, which is much higher than the power-supply voltage, is required, such as 8V and 11V. Therefore, charge pump circuits, which are used to generate a high voltage for programming and erasing from a low power-supply voltage, are widely used in memories.
FIG. 1 schematically illustrates a structural diagram of a two-stage Dickson charge pump. Referring to FIG. 1, each voltage boosting stage in the two-stage Dickson charge pump includes an N-type Metal-Oxide-Semiconductor (NMOS) tube with a connection mode in a diode (i.e., a gate electrode is connected with a drain electrode) and a capacitor which has its one end connected to a source electrode of the NMOS tube and another end connected to a clock oscillator circuit. Capacitors in the two voltage boosting stages are coupling capacitors with a same capacitance. The two clock oscillator circuits generate two-phase nonoverlapping clock signals φ and φ. The amplitudes of the two-phase nonoverlapping clock signals are generally equal to a power-supply voltage VDD. During operation of the charge pump, when φ is of a low level, the power supply VDD charges C1 through the NMOS tube; when φ is of a high level, an upper plate voltage of C1 changes to 2*VDD and C2 is charged. As such, charges are transmitted from a left side to a right side. When φ turns to a low level again, since the NMOS tube only allows charges to flow in one direction, the charges cannot be transmitted from the right side to the left side. Therefore, with an increased number of stages of the charge pump, charges are transmitted from the power supply to an output terminal, so that a desired high voltage is obtained.
FIG. 2 schematically illustrates a structural diagram of a charge pump circuit provided in a memory. Referring to FIG. 2, an erasing operation on a memory array is taken as an example. When an erasing operation needs to be performed on a memory unit in the memory array 16, a high output voltage VEP of the charge pump circuit is provided to a decoding circuit 15 through an erasing control unit 14 as a bias voltage. The decoding circuit 15 is adapted to provide an erasing voltage to the memory array 16. The charge pump circuit includes: a clock driving unit 11, a voltage boosting unit 12, a boosting swing control unit 13 and an adjusting transistor MN1. The clock driving unit 11 is adapted to output a clock driving signal CLK having a fixed frequency. Driven by the clock driving signal CLK, the voltage boosting unit 12 outputs a boosted voltage HVE. The voltage boosting unit 12 may have the same structure as the two-stage Dickson charge pump shown in FIG. 1. The clock driving signal CLK is the two-phase nonoverlapping clock signals φ and φ and the boosted voltage HVE is the high voltage Vout in FIG. 1. The boosting swing control unit 13 is adapted to output a boosting swing control signal GRAMP according to the boosted voltage HVE to control a gate electrode of the adjusting transistor MN1, so as to limit a boosting rate of the high output voltage VEP of a source electrode of the adjusting transistor MN1 and avoid a reliability problem on a gate oxide layer of the memory unit which may be caused by excessively rapid boosting of the high output voltage VEP. To reduce a voltage loss, the adjusting transistor MN1 is generally a zero-threshold NMOS tube, which has a very low voltage threshold close to zero and is called native NMOS.
FIG. 3 schematically illustrates waveforms of output signals of various units in the charge pump circuit shown in FIG. 2. After the charge pump circuit is started, the clock driving unit 11 begins to output the clock driving signal CLK having the fixed frequency. Driven by the clock driving signal CLK, the boosted voltage HVE output by the voltage boosting unit 12 becomes stable after a time period. Under the control of the boosting swing control signal GRAMP output by the boosting swing control unit 13, a boosting rate of the high output voltage VEP of the charge pump circuit slows down gradually.
In a low power consumption system, a peak current denotes to a current flowing in a system in one micro second. Generally, the peak current cannot be higher than 1 mA in the system. In conventional technologies, referring to FIG. 1 and FIG. 2, to control the peak current in a required range, the clock driving signal CLK output by the clock driving unit 11 has a low frequency. When the memory unit is programmed or erased, the decoding circuit 15 and the memory array 16 have leakage currents therein. The sum of the leakage currents is a leakage current load which provides the voltage for programming or erasing in the charge pump circuit. When the frequency of the clock driving signal CLK output by the clock driving unit 11 gradually lows down, to satisfy a requirement on the leakage current load and keep a charge transfer amount among stages of the charge pump circuit unchanged, a capacitor with great capacitance is required in each stage of charge pump circuit to store a large amount of charges. However, the capacitor with great capacitance may increase a size of the charge pump circuit, which does not satisfy a high-level integration of a circuit. Therefore, a charge pump circuit with a small size and low power consumption is desired.
More information about a charge pump circuit with low power consumption can be found in a Chinese patent application No. 03156438.0 and entitled “charge pump circuit with high precision and low power consumption”.